1. Field of the Invention
The present invention relates to a communication method utilizing a time-divisionally multiplexed channel highway and a digital communication apparatus employed in, for example, a key telephone system for realizing the same.
2. Description of the Related Art
As shown in FIG. 1, a conventional digital communication apparatus employed in a key telephone system comprises a main unit 1 and a plurality of telephone sets 2i (i=a to n) connected to main unit 1. Telephone set 2a can be assumed to be a line-wire telephone, and telephone set 2j (j=b to n) can be assumed to be an extension telephone. Up channel highway 10-1 and down channel highway 10-2 are independently formed in main unit 1 and connected by time switch (TSW) 11. Telephone set 2i is connected to highways 10-1 and 10-2 through interface circuit (INF) 12i and codec 13i.
Each interface circuit 12i is connected to corresponding telephone set 2i through a telephone line, supplies power to telephone set 2i and transmits/receives a control signal to/from telephone set 2i. Each codec 13i includes transmitting terminal Tx and receiving terminal Rx for PCM code data, and terminals Tx and Rx are connected to highways 10-1 and 10-2, respectively. Codec 13i samples a voice analog signal from telephone set 2i at, e.g., 8 kHz. The sampled signal is converted into 8-bit PCM code data in accordance with .mu./L law, and the converted code is supplied to a predetermined time slot of highway 10-1 through terminal Tx. At the same time, codec 13i converts PCM code data received at terminal Rx from the predetermined time slot of highway 10-2 into a voice analog signal in a manner opposite to that described above. The converted signal is supplied to corresponding telephone set 2i. That is, codec 13i simultaneously performs transmission and reception.
In each codec, a time slot for transmitting/receiving PCM code data is determined in accordance with time slot signal TSS(i) supplied to transmitting time slot signal input terminal TxTS and receiving time slot signal input terminal RxTS and clock signal PHCLK supplied to clock input terminal CLK. Signal TSS(i) is supplied from TS assigner 14i provided in correspondence to each codec. Signal PHCLK is supplied from timing signal generator 16 directly to terminal CLK.
An address (ADRSi) is assigned to each TS assigner 14i. Assigner 14i determines the time slot signal TSS(i) in accordance with the address (ADRSi) and input frame signal PHFS and clock signal PHCLK. Signals PHFS and PHCLK are supplied from generator 16 in accordance with an output from oscillator 15.
Time switch 11 is connected together with interface circuit 12i to CPU 18 and memory (MM) 19 through .mu.P bus 17. CPU 18 controls switch 11 and circuit 12i on the basis of an operation program stored in memory 19. Switch 11 switches time slots on up and down channel highways 10-1 and 10-2 under the control of CPU 18. As a result, a channel is formed from, e.g., caller telephone set 2a to callee telephone set 2b.
Assume that time slot 0 (represented by TxTS=0 and RxTS=0) is fixedly assigned to telephone set 2a, and time slot 1 (represented by TxTS=1 and RxTS=1) is fixedly assigned to telephone set 2b, respectively. Formation of a channel between telephone sets 2a and 2b in this case will be described below with reference to timing charts shown in FIGS. 2A to 2E. Note that the timing charts in FIGS. 2A to 2E correspond to only an operation of telephone set 2a.
As shown in FIGS. 2A to 2C, signal TSS(a) is formed in accordance with signals PHFS and PHCLK supplied from generator 16. Formed signal TSS(a) has a time length of 8 clocks from the leading edge of signal PHFS. Signal TSS(a) is supplied to terminals TxTS and RxTS of codec 13a.
Codec 18a modulates a voice analog signal from telephone set 2a into PCM code data C0 to C7 in time slot 0 designated by signal TSS(a). Modulated data C0 to C7 are supplied to up channel highway 10-1 as up data PHIN sequentially from LSB(C0) to MSB(C7) at the leading edges of signal PHCLK, as shown in FIG. 2D. Up data PHIN supplied in time slot 0 is switched to time slot 1 in switch 11 for codec 13b. This time slot switching is controlled by CPU 18 on the basis of dial number information of telephone set 2b supplied from telephone set 2a prior to communication.
Thereafter, up data PHIN switched to time slot 1 is supplied to down channel highway 10-2 as down data PHOUT. At this time, TS assigner 14b generates signal TSS(b) in accordance with signals PHFS and PHCLK in the same manner as signal TSS(a) and outputs signal TSS(b) to input terminals TxTS and RxTS of codec 13b.
Codec 13b receives data C0 to C7 as down data PHOUT from highway 10-2 at the trailing edges of signal PHCLK in time slot 1 designated by signal TSS(b). Thereafter, codec 13b demodulates received down data PHOUT into a voice analog signal. The demodulated signal is supplied to telephone set 2b through interface circuit 12b. In this manner, the voice from telephone set 2a is supplied to telephone set 2b.
A voice from telephone set 2b is supplied to telephone set 2a in an order opposite to the above one. That is, PCM code data D0 to D7 modulated by codec 13b are supplied as up data PHIN to highway 10-1 in time slot 1. Data PHIN is supplied to highway 10-2 in time slot 0 by switch 11. As described above, when signal TSS(a) of time slot 0 is supplied from TS assigner 14a, codec 13a receives data PHOUT from highway 10-2 sequentially from LSB(D0) to MSB(D7) at the trailing edges of signal PHCLK, as shown in FIG. 2E. Received data PHOUT is demodulated into a voice analog signal. The demodulated signal is supplied to telephone set 2a through interface circuit 12a. In this manner, the voice from telephone set 2b is also supplied to telephone set 2a, thereby enabling communication between operators.
As described above, in the conventional digital communication apparatus, the up and down channel highways are formed independently from each other, and therefore the time switch for switching time slots on both the channel highways must be provided. As is well known, the time switch includes a high-speed buffer memory, a serial/parallel converter, a parallel/serial converter, a control memory, and the like and hence is expensive although a one-tip LSI is developed. If the circuit is constituted by discrete parts, a size of a circuit structure is increased.